View CAT1320_5536903.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 CAT1320, cat1321 supervisory circuits with i 2 c serial 32k cmos eeprom ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 20585, rev. 00 h a l o g e n f r e e tm l e a d f r e e features precision power supply voltage monitor 5v, 3.3v and 3v systems - +5.0v (+/- 5%, +/- 10%) - +3.3v (+/- 5%, +/- 10%) - +3.0v (+/- 10%) active low reset, CAT1320 active high reset, cat1321 valid reset guaranteed at v cc =1v 400khz i 2 c bus 3.0v to 5.5v operation low power cmos technology 64-byte page write buffer 1,000,000 program/erase cycles 100 year data retention 8-pin dip, soic, tssop and tdfn packages industrial temperature range pin configuration description the CAT1320 and cat1321 are complete memory and supervisory solutions for microcontroller-based systems. a 32kbit serial eeprom memory and a system power supervisor with brown-out protection are integrated together in low power cmos technology. memory interface is via a 400khz i 2 c bus. the CAT1320 provides a precision v cc sense circuit and drives an open drain output, reset low whenever v cc falls below the reset threshold voltage. the cat1321 provides a precision vcc sense circuit that drives an open drain output, reset high whenever v cc falls below the reset threshold voltage. the power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. five reset threshold voltages support 5v, 3.3v and 3v systems. if power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, asic or peripherals from operating. reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. with both active high and low reset options, interface to microcontrollers and other ics is simple. in addition, the reset (CAT1320) pin can be used as an input for push-button manual reset capability. the CAT1320/21 memory features a 64-byte page. in addition, hardware data protection is provided by a v cc sense circuit that prevents writes to memory whenever v cc falls below the reset threshold or until v cc reaches the reset threshold during power up. available packages include an 8-pin dip, soic, tssop and 4.9 x 3mm tdfn. pdip (p, l) soic (j, w) tdfn package: 4.9mm x 3mm (rd2, zd2) tssop (u, y) a0 v cc rese t scl sda a1 a2 v ss CAT1320 1 2 3 4 8 7 6 5 v cc reset scl sda cat1321 1 2 3 4 8 7 6 5 a0 a1 a2 v ss a0 v cc rese t scl sda a1 a2 v ss CAT1320 1 2 3 4 8 7 6 5 cat1321 1 2 3 4 8 7 6 5 v cc reset scl sda a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc rese t scl sda CAT1320 a0 a1 a2 v ss v cc rese t scl sda cat1321 a0 a1 a2 v ss 1 2 3 4 8 7 6 5
2 CAT1320, cat1321 advance information doc. no. 25085, rev. 00 pin description reset/ reset reset reset reset reset : reset outputs these are open-drain pins and reset can also be used as a manual reset trigger input. by forcing a reset condition on the pin the device will initiate and maintain a reset condition. the reset pin must be connected through a pull-down resistor and the reset pin must be connected through a pull-up resistor. sda: serial data address the bidirectional serial data/address pin is used to trans- fer all data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. block diagram CAT1320, cat1321 pin functions pin name function reset active low reset input/output (CAT1320) v ss ground sda serial data/address scl clock input reset active high reset output (cat1321) v cc power supply operating temperature range industrial -40?c to 85?c part dash minimum maximum number threshold threshold -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 threshold voltage options scl: serial clock serial clock input. a0, a1, a2: device address inputs when hardwired, up to eight CAT1320/21 devices may be addressed on a single bus system (refer to device addressing). when the pins are left unconnected, the default values are zeros. 32kbit d out ack sense amps shift registers control logic word address buffers start/stop logic eeprom v cc external load column decoders xdec data in storage high voltage/ timing control v ss sda reset controller precision vcc monitor state counters slave address comparators sc l reset (CAT1320) reset (cat1321) a0 a1 a2
3 advance information CAT1320, cat1321 doc no. 25085, rev. 00 d.c. operating characteristics v cc = +3.0v to +5.5v and over the recommended temperature conditions unless otherwise specified. notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. not 100% tested. 2. v il min and v ih max are reference values only and are not tested. absolute maximum ratings temperature under bias .................... -40 c to +85 c storage temperature ........................ -65 c to +105 c voltage on any pin with respect to ground (1) ............. -0.5v to +v cc +2.0v v cc with respect to ground ................ -0.5v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (1) ........................ 100 ma stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. note: (1) output shorted for no more than one second. no more than one output shorted at a time. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a ms t i n u i i l t n e r r u c e g a k a e l t u p n iv n i c c v o t d n g =2 -0 1a i o l t n e r r u c e g a k a e l t u p t u ov n i c c v o t d n g =0 1 -0 1a i 1 c c ) e t i r w ( t n e r r u c y l p p u s r e w o p f l c s z h k 0 0 4 = v c c v 5 . 5 = 3a m i 2 c c ) d a e r ( t n e r r u c y l p p u s r e w o p f l c s z h k 0 0 4 = v c c v 5 . 5 = 1a m i b s t n e r r u c y b d n a t s , v 5 . 5 = c c v v n i c c v r o d n g = 0 4a v l i 2 e g a t l o v w o l t u p n i5 . 0 -c c v x 3 . 0v v h i 2 e g a t l o v h g i h t u p n ic c v x 7 . 05 . 0 + c c vv v l o e g a t l o v w o l t u p t u o , a d s ( t e s e r ) i l o a m 3 = v c c v 0 . 3 = 4 . 0v v h o e g a t l o v h g i h t u p t u o ) t e s e r ( i h o a m 4 . 0 - = v c c v 0 . 3 = - c c v 5 7 . 0 v v h t d l o h s e r h t t e s e r 5 4 - x 2 3 1 t a c v ( c c ) v 5 = 0 5 . 45 7 . 4 v 2 4 - x 2 3 1 t a c v ( c c ) v 5 = 5 2 . 40 5 . 4 0 3 - x 2 3 1 t a c v ( c c ) v 3 . 3 = 0 0 . 35 1 . 3 8 2 - x 2 3 1 t a c v ( c c ) v 3 . 3 = 5 8 . 20 0 . 3 5 2 - x 2 3 1 t a c v ( c c ) v 3 = 5 5 . 20 7 . 2 v d i l a v r 1 v d i l a v t u p t u o t e s e r c c e g a t l o v0 0 . 1v v t r 1 s i s e r e t s y h d l o h s e r h t t e s e r5 1v m
4 CAT1320, cat1321 advance information doc. no. 25085, rev. 00 capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test test conditions max units c out (1) output capacitance v out = 0v 8 pf c in (1) input capacitance v in = 0v 6 pf a.c. characteristics v cc = 3.0v to 5.5v and over the recommended temperature conditions, unless otherwise specified. notes: 1. this parameter is characterized initially and after a design or process change that affects the parameter. not 100% tested. 2. test conditions according to ac test conditions table. 3. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high and the device does not respond to its slave address. e l c y c e t i r w & d a e r y r o m e m 2 l o b m y sr e t e m a r a pn i mx a ms t i n u f l c s y c n e u q e r f k c o l c0 0 4z h k t p s 1 e k i p s r e t l i f t u p n i ) l c s , a d s ( n o i s s e r p p u s 0 0 1s n t w o l d o i r e p w o l k c o l c3 . 1s t h g i h d o i r e p h g i h k c o l c6 . 0s t r 1 e m i t e s i r l c s d n a a d s0 0 3s n t f 1 e m i t l l a f l c s d n a a d s0 0 3s n t a t s ; d h e m i t d l o h n o i t i d n o c t r a t s6 . 0s t a t s ; u s e m i t p u t e s n o i t i d n o c t r a t s ) t r a t s d e t a e p e r a r o f ( 6 . 0s t t a d ; d h e m i t d l o h t u p n i a t a d0s n t t a d ; u s e m i t p u t e s t u p n i a t a d0 0 1s n t o t s ; u s e m i t p u t e s n o i t i d n o c p o t s6 . 0s t a a d i l a v t u o a t a d o t w o l l c s0 0 9s n t h d e m i t d l o h t u o a t a d0 5s n t f u b 1 a e r o f e b e e r f e b t s u m s u b e h t e m i t t r a t s n a c n o i s s i m s n a r t w e n 3 . 1s t c w 3 ) e g a p r o e t y b ( e m i t e l c y c e t i r w5s m
5 advance information CAT1320, cat1321 doc no. 25085, rev. 00 reset circuit a.c. characteristics notes: 1. test conditions according to ac test conditions table. 2. power-up, input reference voltage v cc = v th , reset output reference voltage and load according to ac test conditions table 3. power-down, input reference voltage v cc = v th , reset output reference voltage and load according to ac test conditions table 4. v cc glitch reference voltage = v thmin ; based on characterization data 5. this parameter is characterized initially and after a design or process change that affects the parameter. not 100% tested. 6. t pur and t puw are the delays required from the time v cc is stable until the specified memory operation can be initiated. ac test conditions reliability characteristics symbol parameter reference test method min max units n end (1) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (1) data retention mil-std-883, test method 1008 100 years v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1)(2) latch-up jedec standard 17 100 ma s e g a t l o v e s l u p t u p n iv 2 . 0 c c v 8 . 0 o t c c s e m i t l l a f d n a e s i r t u p n is n 0 1 s e g a t l o v e c n e r e f e r t u p n iv 3 . 0 c c v 7 . 0 , c c s e g a t l o v e c n e r e f e r t u p t u ov 5 . 0 c c d a o l t u p t u o i : e c r u o s t n e r r u c l o ; a m 3 = c l f p 0 0 1 = l o b m y sr e t e m a r a p t s e t s n o i t i d n o c n i mp y tx a ms t i n u t t s r u p t u o e m i t t e s e r2 e t o n0 3 10 0 20 7 2s m t d p r v h t y a l e d t u p t u o t e s e r o t3 e t o n5s t h c t i l g v c c h t d i w e s l u p t c e j e r h c t i l g5 , 4 e t o n0 3s n h c t i l g r my t i n u m m i h c t i l g t e s e r l a u n a m5 e t o n0 0 1s n t w r m h t d i w e s l u p r m5 e t o n5 s g n i m i t p u - r e w o p 6 , 5 l o b m y sr e t e m a r a p t s e t s n o i t i d n o c n i mp y tx a ms t i n u t r u p n o i t a r e p o d a e r o t p u - r e w o p 0 7 2s m t w u p n o i t a r e p o e t i r w o t p u - r e w o p 0 7 2s m notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. not 100% tested. 2. latch-up protection is provided for stresses up to 100ma on input and output pins from -1v to v cc + 1v.
6 CAT1320, cat1321 advance information doc. no. 25085, rev. 00 when reset i/o is driven to the active state, the 200 msec timer will begin to time the reset interval. if external reset is shorter than 200 ms, reset outputs will remain active at least 200 ms. glitches shorter than 100 ns on reset input will not generate a reset pulse. hardware data protection the CAT1320/21 family has been designed to solve many of the data corruption issues that have long been associated with serial eeproms. data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. whenever the device is in a reset condition, the embedded eeprom is disabled for all operations, including write operations. if the reset output is active, in progress communications to the eeprom are aborted and no new communications are allowed. in this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. an internal write cycle initiated before the reset condition can be successfully finished if there is enough time (5ms) before vcc reaches the minimum value of 2v. device operation reset controller description the CAT1320/21 precision reset controllers ensure correct system operation during brownout and power up/down conditions. they are configured with open- drain reset /reset outputs. during power-up, the reset /reset output remains active until v cc reaches the v th threshold and will continue driving the outputs for approximately 200ms (t purst ) after reaching v th . after the t purst timeout interval, the device will cease to drive the reset output. at this point the reset output will be pulled up or down by their respective pull up/down resistors. during power-down, the reset /reset output will be active when v cc falls below v th . the reset /reset output will be valid so long as v cc is >1.0v (v rvalid ). the device is designed to ignore the fast negative going v cc transient pulses (glitches). reset output timing is shown in figure 1. manual reset operation the reset pin can operate as reset output and manual reset input. the input is edge triggered; that is, the reset input will initiate a reset timeout after detecting a high to low transition. figure 1. reset/reset output timing glitch t v cc purst t purst t rpd t rvalid v v th reset reset rpd t
7 advance information CAT1320, cat1321 doc no. 25085, rev. 00 figure 2. reset reset reset reset reset as manual reset input operation and timing reset t purst t mrw reset (input) (output) t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh figure 3. bus timing
8 CAT1320, cat1321 advance information doc. no. 25085, rev. 00 embedded eeprom operation the CAT1320 and cat1321 feature a 32kbit embedded serial eeprom that supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the CAT1320/21 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the master begins a transmission by sending a start condition. the master sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the CAT1320/21 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the CAT1320/21 then performs a read or write operation depending on the r/ w bit. t wr stop condition start condition address ack 8th bit byte n scl sda figure 4. write cycle timing
9 advance information CAT1320, cat1321 doc no. 25085, rev. 00 acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the CAT1320/21 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. when the CAT1320/21 begins a read mode it transmits 8 bits of data, releases the sda line and monitors the line for an acknowledge. once it receives this acknowledge, the CAT1320/21 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends two 8-bit address bytes that are to be written into the address pointers of the device. after receiving another acknowledge from the slave, the master device transmits the data to be written into the addressed memory location. the CAT1320/ 21 acknowledges once more and the master generates the stop condition. at this time, the device begins an internal programming cycle to non-volatile memory. while the cycle is in progress, the device will not respond to any request from the master device. figure 7. slave address bits cat default configuration 1010a2a1a0r/w start bit sda stop bit scl figure 5. start/stop timing acknowledge 1 start scl from master 89 data output from transmitter data output from receiver figure 6. acknowledge timing
10 CAT1320, cat1321 advance information doc. no. 25085, rev. 00 figure 9. page write timing *=don t care bit figure 8. byte write timing *=don t care bit page write the CAT1320/21 writes up to 64 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the master is allowed to send up to additional 63 bytes. after each byte has been transmitted, the CAT1320/21 will respond with an acknowledge and internally increment the lower order address bits by one. the high order bits remain unchanged. if the master transmits more than 64 bytes before sending the stop condition, the address counter wraps around, and previously transmitted data will be overwritten. when all 64 bytes are received, and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the CAT1320/21 in a single write cycle. * a 15 a 8 slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t a 7 a 0 byte address a c k * * * a 15 a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 a 0 byte address data n+63 data a c k s t o p a c k data n a c k p a c k * ** *
11 advance information CAT1320, cat1321 doc no. 25085, rev. 00 acknowledge polling disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host s write opration, the CAT1320/21 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the device is still busy with the write operation, no ack will be returned. if a write operation has completed, an ack will be returned and the host can then proceed with the next read or write operation. read operations the read operation for the CAT1320/21 is initiated in the same manner as the write operation with one exception, that r/ w bit is set to one. three different read operations are possible: immediate/current address read, selective/random read and sequential read. scl sda 8th bit stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t figure 10. immediate address read timing
12 CAT1320, cat1321 advance information doc. no. 25085, rev. 00 figure 11. selective read timing *=don t care bit immediate/current address read the CAT1320 and cat1321 address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n+1. for all devices, n=e=4,095. the counter will wrap around to zero and continue to clock out valid data. after the CAT1320 and cat1321 receives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. the master device does not send an acknowledge, but will generate a stop condition. selective/random read selective/random read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte addresses of the location it wishes to read. after the CAT1320 and cat1321 acknowledges, the master device sends the start condition and the slave address again, this time with the r/ w bit set to one. the CAT1320 and cat1321 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the CAT1320 and cat1321 sends the inital 8-bit byte requested, the master will responds with an acknowledge which tells the device it requires more data. the CAT1320 and cat1321 will continue to output an 8-bit byte for each acknowledge, thus sending the stop condition. the data being transmitted from the CAT1320 and cat1321 is sent sequentially with the data from address n followed by data from address n+1. the read operation address counter increments all of the CAT1320 and cat1321 address bits so that the entire memory array can be read during one operation. bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address figure 12. sequential read timing a 15 a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 a 0 byte address slave address s a c k n o a c k s t a r t data p s t o p * * * *
13 advance information CAT1320, cat1321 doc no. 25085, rev. 00 8-lead pdip (p, l) package outlines 0.180 (4.57) max 0.015 (0.38) 0.100 (2.54) bsc 0.014 (0.36) 0.022 (0.56) d 0.245 (6.17) 0.295 (7.49) 0.045 (1.14) 0.060 (1.52) 0.110 (2.79) 0.150 (3.81) 0.120 (3.05) 0.150 (3.81) 0.300 (7.62) 0.325 (8.26) 0.310 (7.87) 0.380 (9.65) notes: 1. complies with jedec publication 95 ms001 dimensions; however, some of the dimensions may be more stringent. 2. all linear dimensions are in inches and parenthetically in millimeters. dimension d pkg min max 8l 0.355 (9.02) 0.400 (10.16)
14 CAT1320, cat1321 advance information doc. no. 25085, rev. 00 8-lead soic (j, w) package outlines notes: 1. complies with jedec publication 95 ms-012 dimensions; however, some dimensions may be more stringent. 2. all linear dimensions are in inches and parenthetically in millimeters. 3. lead coplanarity is 0.004" (0.102mm) maximum. dimension d pkg min max 8l 0.1890(4.80) 0.1968(5.00) 0.1497 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.1890 (4.80) 0.1968 (5.00) 0.0532 (1.35) 0.0688 (1.75) 0.0040 (0.10) 0.0098 (0.25) 0.013 (0.33) 0.020 (0.51) 0.050 (1.27) bsc 0.016 (0.40) 0.050 (1.27) 0.0099 (0.25) 0.0196 (0.50) x 46 0.0075 (0.19) 0.0098 (0.25) 0 - 8
15 advance information CAT1320, cat1321 doc no. 25085, rev. 00 8-lead tssop (u, y) package outlines
16 CAT1320, cat1321 advance information doc. no. 25085, rev. 00 8-pad tdfn 4.9x3mm package (rd2, zd2) package outlines d 0.08 c f 0.10 c 0.10m c a b 0.15 8 5 a 5 b 8 3.00 + 0.15 2.00 + 0.15 0.10 0.15 0.20 0.25 pin 1 id 0.60 + 0.10 (8x) d 0.15 c 2x 4.90 + 0.10 (5) 1 pin 1 index area 3.00 + 0.10 (s) 4 2x d c 4 0.30 + 0.05 (8x) 8x j 1.95 ref. (2x) 1 0.65 typ. (6x) 0.75 + 0.05 0.0-0.05 8x 0.20 ref. c note: 1. all dimension are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.08mm. 3. warpage shall not exceed 0.10mm. 4. package length / package width are considered as special characteristic(s). 5. refer to jedec mo-229, footprints are compatible to 8 msop.
17 advance information CAT1320, cat1321 doc no. 25085, rev. 00 ordering information note: (1) the device used in the above example is a CAT1320ji-30te13 (supervisory circuit with i 2 c serial 32k cmos eeprom, soic, industrial temperature, 3.0-3.15v reset threshold voltage, tape and reel). 1320 temperature range i = industrial (-40 ? c to 85 ? c) prefix device # suffix j i te13 product number 1320: 32k tape & reel te13: 2000/reel soic: 2000/reel tssop: 2000/reel tdfn: 2000/reel package p: pdip j: soic u: tssop rd2: 8-pad tdfn (4.9mmx3mm) l: pdip (lead free, halogen free) w: soic, jedec (lead free, halogen free) y: tssop (lead free, halogen free) zd2: tdfn 4.9x3mm (lead free, halogen free) -30 cat reset threshold voltage 45: 4.5-4.75v 42: 4.25-4.5v 30: 3.0-3.15v 28: 2.85-3.0v 25: 2.55-2.7v optional company id 1321: 32k
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 25085 revison: 00 issue date: 1/25/05 revision history date rev. reason 1/25/2005 00 initial issue

▲Up To Search▲

Price & Availability of CAT1320

	To Download CAT1320 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .